1. Field of the Invention
The present invention relates to the field of integrated circuit (IC) design methodology. More particularly, the present invention relates to the field of the IC design process and the conversion process of producing register transfer level definition of ICs from a gate level definition of the ICs.
2. Description of the Related Art
To design and produce an integrated circuit (IC), a specification document is first drafted, and after many intermediate steps, layout level design, performing the functions as defined by the specification, is produced. The layout level design is the lowest level description of the IC design. In the layout level design, the transistors are represented as geometric figures with physical dimensions such as length, width and position.
The IC design process involves complex subprocesses requiring many intermediate steps. At each of these intermediate steps, the IC design is represented at a different level of specificity.
One of the higher level descriptions of an IC design is the Register Transfer Level (RTL) design. In the RTL, variables and data operators represent the IC components such as registers and functional blocks of the sections of the IC. Being a more generic high-level description of the IC, the RTL design could be easily mapped across different IC design process technologies.
The next lower level description of IC in the design process is the Logic Level design at which the IC is defined as a set of interconnecting logic gates such as AND, OR gates and memory components such as flip-flops. This level is also called the Gate Netlist Level, and the IC design at this level of specificity will be referred to as the "Netlist" in this document. Netlist is a more specific definition of the IC design than a RTL design. A Netlist design is much less portable for use in other IC design process technologies because Netlist is technology and process specific. Also, making modifications and upgrading designs in Netlist form is cumbersome. On the other hand, modifying and upgrading RTL designs is relatively easy. Hence, it is desirable to have designs in the RTL form.
The process of translating an RTL design into a Netlist design is commonly referred to as "synthesis." Because the RTL methodology of expressing designs is a relatively new concept, most earlier IC designs were hand-tuned or hand-crafted at the Netlist level without having a corresponding RTL designs. In fact, many of the current IC designs exist only as Netlist definitions. Since tremendous effort has gone into these designs and many of these designs have to be used in newer process technologies, obtaining a RTL description of these designs would prove to be very useful.
As the IC design process technology developed over the years and the IC designs became increasingly larger and more complex, the industry developed many different process technologies to implement IC designs. Most of these process technologies support synthesis of RTL designs into their corresponding Netlist designs and, eventually, Layout Level designs. However, the IC designs existing only at the Netlist level cannot take advantage of the new process technologies because Netlists are highly process and technology dependent. Once a design is mapped to a one process technology it is very difficult to migrate to another process technology. For example, at the layout level a NAND gate in one process technology would inherit different electrical characteristics such as capacitance, and rise time, etc. But when migrating to another technology the NAND gates available in the new technology would not essentially have the same electrical characteristics as the previous one.
The present invention discloses a method to overcome this problem by converting, or reverse-synthesizing, Netlist designs into corresponding RTL designs defining the same IC. After reverse-synthesizing Gate Netlist definitions into corresponding RTL designs, the IC design which was defined using only the Netlist definition can now be ported to other, new process technologies.
A company called Chrysalys offers a reverse-synthesis tool to convert Netlist designs to behavioral level designs which are similar to RTL designs. However, Chrysalys' reverse-synthesis is performed using a mathematical equivalence method and the resultant behavioral level designs are generally not synthesizable using new IC design process technologies.
The only other remaining option for reverse-synthesizing Netlist designs into RTL designs is to manually study the Netlist to hand-generate the corresponding RTL design. However, this is very time consuming, lacks a refined methodology, and is prone to error.